Avago Technologies LSI53C1000R - Manual (Page 266)

5-24 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
A[6:0] Register Address – A[6:0] [22:16]
It is possible to change register values from SCRIPTS in
read-modify-write cycles or move to/from
SCSI First Byte Received (SFBR) cycles. A[6:0] selects
an 8-bit source/destination register within the
LSI53C1000R.
IMMD Immediate Data [15:8]
This 8-bit value is used as a second operand in logical
and arithmetic functions.
A7 Upper Register Address Line [A7] 7
This bit accesses registers 0x80–0xFF.
R Reserved [6:0]
Must be 0.
5.4.2 Second Dword
This section describes the second Dword of the Read/Write Instruction
register.
Figure 5.8 Read/Write Instruction – Second Dword
DA Destination Address [31:0]
This field contains the 32-bit destination address where
the data is to move.
5.4.3 Read-Modify-Write Cycles
During these cycles the register is read, the selected operation is
performed, and the result is written back to the source register.
The Add operation increments or decrements register values (or memory
values if used in conjunction with a Memory-to-Register Move operation)
for use as loop counters.
Subtraction is not available when SCSI First Byte Received (SFBR) is
used instead of data8 in the instruction syntax. To subtract one value
from another when using SFBR, first XOR the value to subtract
31 0
DSPS Register