Avago Technologies LSI53C1000R User Manual
Page 81
SCSI Functional Description
2-51
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
INTA/ pin. Because no interrupt is generated, future interrupts move into
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
instead of stacking behind another interrupt. When another interrupt
condition occurs, the bit corresponding to the earlier masked nonfatal
interrupt is set.
A related situation to interrupt stacking is when two interrupts occur
simultaneously. Because stacking does not occur until the SIP or DIP bits
are set, there is a small timing window in which multiple interrupts can occur
but are not stacked. These could be multiple SCSI interrupts (SIP set),
multiple DMA interrupts (DIP set), or multiple SCSI and multiple DMA
interrupts (both SIP and DIP set).
As previously mentioned, DMA interrupts do not attempt to flush the
FIFOs before generating the interrupt. It is important to set either the
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is
because any future SCSI interrupts are not posted until the DMA FIFO
is cleared of data. These “locked out” SCSI interrupts are posted as soon
as the DMA FIFO is empty.
2.2.16.6 Halting in an Orderly Fashion
When an interrupt occurs, the LSI53C1000R attempts to halt in an
orderly fashion.
•
If the interrupt occurs in the middle of an instruction fetch, the fetch
is completed, except in the case of a Bus Fault. Execution does not
begin, but the DSP points to the next instruction because it is
updated when the current instruction is fetched.
•
If the DMA direction is a write to memory and a SCSI interrupt
occurs, the LSI53C1000R attempts to flush the DMA FIFO to
memory before halting. Under any other circumstances, only the
current cycle is completed before halting, so the DFE bit in
should be checked to determine if any data
remains in the DMA FIFO.
•
SCSI SREQ/SACK handshakes that are in progress are completed
before halting.
•
The LSI53C1000R attempts to clean up any outstanding
synchronous offset before halting.