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Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal User Manual

Page 464

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Instruction Execution Times

Appendix C
Memory Usage,

C–10

Instruction Execution Times for the SLC 5/02 Processor Series C
and Later

The SLC 5/02 series C processor performance is on the average 40% faster
than that of the SLC 5/02 series B processor. The table below lists the
instruction execution times for the SLC 5/02 series C processor.

MSG

48

180

MUL

7

140

MVM

7

71

NEG

7

68

NEQ

38

38

NOT

7

42

OR

7

55

OSR

7

20

OTE

11

11

OTL

11

11

OTU

11

11

PID

90

3600

REF

4

240 +
180 per word

RES

7

26

RET

7

20

RPI

7

240

RTO

30

86

SBR

1

4

SCL

7

480

SQC

36

137

SQL

36

135

SQO

36

137

SQR

7

162

STD

4

9

STE

4

9

STS

7

72

SUB

7

77

SUS

7

7

SVC

4

240

TND

7

22

TOD

7

122

TOF

36

86

TON

36

83

XIC

2.4

2.4

XIO

2.4

2.4

XOR

7

55

Execution Time

in Microseconds

(approx.)

False

True

Instruction

(Series C

SLC 5/02)

ADD

7

76

AND

7

55

BSL

36

89 + 14 per word

BSR

36

83 + 14 per word

CLR

7

26

COP

7

29 + 13 per word

CTD

7

69

CTU

7

69

DCD

7

50

DDV

7

392

DIV

7

242

EQU

38

38

FFL

51

150

FFU

51

150 +
11 x position value

FLL

7

25 + 8 per word

FRD

7

136

GEQ

38

38

GRT

38

38

IID

7

39

IIE

7

42

IIM

7

340

INT

0

0

IOM

7

465

JMP

7

23

JSR

7

28

LBL

1

4

LEQ

38

38

LES

38

38

LFL

51

150

LFU

51

180

LIM

7

45

MCR

6

6

MEQ

7

47

MOV

7

14

Execution Time

in Microseconds

(approx.)

False

True

Instruction

(Series C

SLC 5/02)

For the rung example below:
1) If instruction 1 is false, instructions 2, 3, 4, 5, 6, 7

take zero execution time.
Execution time = 2.4 + 11 = 13.4 microseconds.

2) If instruction 1 is true, 2 is true, and 6 is true, then

instructions 3, 4, 5, 7 take zero execution time.
Execution time = 2.4 + 2.4 + 2.4 + 11 = 18.2
microseconds.

] [

1

( )

8

] [

2

] [

6

] [

3

] [

4

] [

5

] [

7

These instructions take zero execution time if
they are preceded by conditions that guarantee
the state of the rung. Rung logic is solved left
to right. Branches are solved top to bottom.

This only includes the amount of time needed to
“set up” the operation requested. It does not
include the time it takes to service the actual
communications.