Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal - Manual (Page 243)

Chapter 17
Timer and Counter Instructions
17–11
The HSC’s status bits and accumulator are non-retentive. At power-up or
Run mode entry, the HSC instruction will clear the status bits, clear the
accumulator, and load the preset value.
Instruction Parameters
Address C5:0 is the HSC counter 3-word element.
CU CD DN OV UN UA Not Used
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Preset Value
Accumulated Value
CU = Indicates enable/disable status of the HSC
CD = Does not apply to HSC
DN = Done bit
OV = Overflow bit
UN = Does not apply to HSC
UA = Update accumulator
•
Word 0 contains the status bits of the HSC instruction:
– Bit 10 (UA) updates the accumulator word of the HSC to reflect the
immediate state of the HSC when true.
– Bit 12 (OV) indicates if a HSC overflow has occurred.
– Bit 13 (DN) indicates if the HSC preset value has been reached.
– Bit 15 (CU) shows the enable/disable state of the HSC.
•
Word 1 contains the preset value that is loaded into the HSC when the
RES instruction is executed, when the done bit is set, or when powerup
takes place. The valid range is 1 – 32767.
•
Word 2 contains the HSC accumulated value. This word is updated each
time the HSC instruction is evaluated and when the update accumulator
bit is set using an OTE instruction. This accumulator is read only. Any
value written to the accumulator is overwritten by the actual high–speed
counter on instruction evaluation, reset, or Run mode entry.
Application Example
In the figure that follows, rungs 6, 16, and 31 of the main program file each
consist of an XIC instruction addressed to the HSC done bit and a JSR
instruction. These rungs poll the status of the HSC done bit. When the DN
bit is set at any of these poll points, program execution moves to subroutine
file 3, executing the HSC logic. After the HSC logic is executed, the DN bit
is reset by an unlatch instruction, and program execution returns to the main
program file.