Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal - Manual (Page 378)

Chapter 27
The Status File
27–10
Address Description 5/02
5/01,
Fixed
S:2/14 Math Overflow Selection Bit
Applies to Series C and later SLC 5/02 processors only.
Set this bit when you intend to use 32-bit addition and subtraction.
When S:2/14 is set, and the result of an ADD, SUB, MUL, or DIV
instruction cannot be represented in the destination address
(underflow or overflow),
•
the overflow bit S:0/1 is set,
•
the overflow trap bit S:5/0 is set, and
•
the destination address contains the unsigned truncated
least significant 16 bits of the result.
The default condition of S:2/14 is reset (0). This provides the same
operation as that of the Series B SLC 5/02 processor. When S:2/14
is reset, and the result of an ADD, SUB, MUL, or DIV instruction
cannot be represented in the destination address (underflow or
overflow),
•
the overflow bit S:0/1 is set,
•
the overflow trap bit S:5/0 is set, and
•
the destination address contains 32767 if the result is
positive or – 32768 if the result is negative.
Note that the status of bit S:2/14 has no effect on the DDV instruction.
Also, it has no effect on the math register content when using MUL
and DIV instructions.
To program this feature, use the EDT_DAT function to set/clear this
bit. To provide protection from inadvertent data monitor alteration of
your selection, program an unconditional OTL instruction at address
S:2/14 to ensure the new math overflow operation, or program an
unconditional OTU instruction at address S:2/14 to ensure the original
math overflow operation.
See chapter 20 for an application example of 32-bit signed math.
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