Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal - Manual (Page 422)

Interrupts – 5/02 Processor Only
Chapter 30
Understanding Selectable Timed
30–2
STI Subroutine Content
For identification of your STI subroutine, include an INT instruction as the
first instruction. This identifies the subroutine as an interrupt subroutine
versus a normal subroutine.
The STI subroutine will contain the rungs of your application logic. You can
program any instruction inside the STI subroutine except a TND, REF, or
SVC instruction. IIM or IOM instructions are needed in an STI subroutine if
your application requires immediate update of input or output points. End
the STI subroutine with an RET instruction.
JSR stack depth is limited to 3. That is, you may call other subroutines to a
level 3 deep from an STI subroutine.
Interrupt Occurrences
STI interrupts can occur at any point in your program, but not necessarily at
the same point on successive interrupts. Interrupts can only occur between
instructions in your program, inside the I/O scan (between slots), or between
the servicing of communications packets. STI execution time adds directly
to the overall scan time.
Processor Overhead
Communication
Output Scan
Program Scan
Input Scan Between slot updates
Between instruction executions
Between slot updates
Between communication packets
Events in the processor operating cycle
STI interrupts can occur:
Interrupt Latency
The interrupt latency (interval between the STI timeout and the start of the
interrupt subroutine) is 3.7 milliseconds max. for the SLC 5/02 series B
processor, and 2.4 milliseconds max. for the SLC 5/02 series C and later.
During the latency period, the processor is performing operations that cannot
be disturbed by the STI interrupt function.