Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal - Manual (Page 281)

Chapter 20
Math Instructions
20–5
With the Series C SLC 5/02 processor, you have the option of performing
16-bit signed integer addition and subtraction (same as Series B SLC 5/02
processors) or 32-bit signed integer addition and subtraction. This is
facilitated by status file bit S:2/14, the Math Overflow Selection Bit.
Bit S:2/14 Math Overflow Selection
Set this bit when you intend to use 32-bit addition and subtraction. When
S:2/14 is set, and the result of an ADD, SUB, MUL, or DIV instruction
cannot be represented in the destination address (due to a math underflow or
overflow):
•
The overflow bit S:0/1 is set.
•
The overflow trap bit S:5/0 is set.
•
The destination address contains the unsigned truncated least significant
16 bits of the result. When combined with the operation of the carry bit,
the unsigned truncated value in the destination allows you to retain the
true value of the result.
The default condition of S:2/14 is reset (0). This provides the same operation
as that of the Series B SLC 5/02 processor. When S:2/14 is reset, and the
result of an ADD, SUB, MUL, or DIV instruction cannot be represented in
the destination address (underflow or overflow):
•
The overflow bit S:0/1 is set.
•
The overflow trap bit S:5/0 is set.
•
The destination address contains 32767 if the result is positive or –32768
if the result is negative.
Note that the status of bit S:2/14 has no effect on the DDV instruction. Also,
it has no effect on the math register content when using MUL and DIV
instructions.
Example of 32-Bit Addition
The following example shows how a 16-bit signed integer is added to a
32-bit signed integer. Remember that S:2/14 must be set for 32-bit addition.
Note that in this program, the value of the most significant 16 bits (B3:3) of
the 32-bit number is increased by 1 if the carry bit S:0/0 is set and it is
decreased by 1 if the number being added (B3:1) is negative.
To avoid a major error from occurring at the end of the scan, you must
unlatch overflow trap bit S:5/0 as shown.
32-Bit Addition and
Subtraction–Series C and
Later SLC 5/02 Processors