Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal - Manual (Page 434)

5/02 Processor Only
Chapter 31
Understanding I/O Interrupts –
31–4
Status File Data Saved
Data in the following words is saved on entry to the I/O interrupt subroutine
and re-written upon exiting the I/O interrupt subroutine.
•
S:0 Arithmetic flags
•
S:13 and S:14 Math register
•
S:24 Index register
The I/O interrupt parameters below have status file addresses. They are
described here and also in chapter 27.
S:11 and S:12 I/O Slot Enables – Read/Write. These words are bit
mapped to the 30 I/O slots. Bits S:11/1 through S:12/14 refer to slots
1 through 30. Bits S:11/0 and S:12/15 are reserved. The enable bit
associated with an interrupting slot must be set when an interrupt
occurs. Otherwise a major fault will occur. See chapter 27 for more
details. Changes made to these bits using the EDT_DAT function
take effect at the next end of scan.
S:27 and S:28 I/O Interrupt Enables – Read/Write. These words
are bit mapped to the 30 I/O slots. Bits S:27/1 through S:28/14 refer
to slots 1 through 30. Bits S:27/0 and S:28/15 are reserved. The
enable bit associated with an interrupting slot must be set when the
interrupt occurs to allow the corresponding ISR to execute.
Otherwise the ISR will not execute and the associated I/O slot
interrupt pending bit will be set. Changes made to these bits using
the EDT_DAT function take effect at the next end of scan.
S:25 and S:26 I/O Interrupt Pending Bits – Read only. These
words are bit mapped to the 30 I/O slots. Bits S:25/1 through
S:26/14 refer to slots 1 through 30. Bits S:25/0 and S:26/15 are
reserved. The pending bit associated with an interrupting slot is set
when the corresponding I/O slot interrupt enable bit is clear at the
time of an interrupt request. It is cleared when the corresponding I/O
event interrupt enable bit is set, or when an associated RPI
instruction is executed. The pending bit for an executing I/O
interrupt subroutine remains clear when the ISR is interrupted by an
STI or fault routine. Likewise, the pending bit remains clear if
interrupt service is requested at the time that a higher or equal
priority interrupt is executing (fault routine, STI, or other ISR).
I/O Interrupt Parameters