Using arithmetic status bits, Ladder logic filtering of bcd input devices, Math register (when used) – Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal User Manual

Page 292

Chapter 20
Math Instructions

20–16

Using Arithmetic Status Bits

C always reset

V set if a non-BCD value is contained at the source or the value to be

converted is greater than 32,767; otherwise reset. Overflow results in a
minor error.

Z set when destination value is zero

S always reset

Math Register (When Used)

Used as the source for converting the entire number range of a register.

Ladder Logic Filtering of BCD Input Devices

We recommend that you always provide ladder logic filtering of all BCD
input devices prior to executing the FRD instruction. The slightest difference
in point–to–point input filter delay can cause the FRD instruction to fault due
to conversion of a non–BCD digit. An example of filtering is shown below.

The above rungs cause the processor to verify that the value at slot 2 (I:2)
remains the same for two consecutive scans before the FRD instruction is
executed. This prevents the FRD instruction from converting a non–BCD
value during an input value change.

FRD

FROM BCD
Source

I:2

Dest

N7:2

MOV

MOVE
Source

I:2

Dest

N7:1

]/[

S:1

EQU

EQUAL
Source A

N7:1

Source B

I:2