Figure4.4 lsi53c875jb pin diagram (top view), Lsi53c875jb pin diagram (top view), Figure 4.4 – Avago Technologies LSI8751D User Manual
Page 97
4-5
Figure 4.4
LSI53C875JB Pin Diagram (Top View)
Note: Pins F7, G6, G7, G8, and H7 are connected to the die pad.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
C_BE3/
AD24
AD27
AD29
VDD-C
CLK
MCE/
MAS0/
VSS
TCK
SDIR2
SDIR5
SDIR6
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
IDSEL
NC
VSS
AD28
AD31
RST/
MDE/
MAS1/
SDIR14
VDD
VSS
NC
SDIR7
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
AD21
AD23
VSS
AD26
AD30
VSS-C
MWE/
SDIR12
SDIR15
SDIR1
SDIR4
VDD-S
SD13/
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
VSS
VDD-1
AD20
AD25
VDD-1
GNT/
TDI
SDIR13
SDIR0
SDIRP0
SD12
VSS-S
SD15/
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
AD16
AD17
AD18
AD19
AD22
REQ/
SERR/
VDD
SDIR3
SD14/
SD0/
SD1/
VSS-S
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
IRDY/
FRAME/
C_BE2/
VSS
VSS
VSS
NC
SDP1/
SD2/
SD3/
SD4/
VSS-S
SD5/
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
VDD
DEVSEL/
TRDY/
STOP/
VSS
NC
NC
NC
SD6/
SD7/
VSS-S
SATN/
SDP0/
H1
H2
H3
H4
H5
H5
H7
H8
H9
H10
H11
H12
H13
PAR
PERR/
C-BE1/
VSS
AD15
AD12
NC
DIFFSENS
SBSY/
SSEL/
SMSG/
SRST/
SACK/
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
AD14
AD13
VSS
AD10
VDD-1
TD0
VDD
GPIO_
MAS2/
SD11/
SD8/
SREQ/
SC_D/
VSS-S
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
VDD-1
AD11
VSS
C_BE0/
AD1
GPIO1_
MASTER/
MAD4
MAD0
IGS
VSS
SD9/
VSS-S
SI_0/
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
AD9
AD8
AD4
AD2
VDD-C
VSS-C
MAD7
MAD1
GPIO4
RSTDIR
VDD-S
SDIR8
SD10/
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
AD7
NC
AD5
VSS
IRQ/
SCLK
MAD6
MAD3
GPIO3
VDD
BSYDIR
NC
SDIR9
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
AD6
VSS
AD3
AD0
GPIO_
FETCH/
TMS
MAD5
MAD2
VSS
TGS
SELDIR
SDIR11
SDIR10