Avago Technologies LSI8751D - Manual (Page 218)

6-22 Instruction Set of the I/O Processor
O[2:0] Operator [26:24]
These bits are used in conjunction with the opcode bits
to determine which instruction is currently selected. Refer
to
Table 6.1 for field definitions.
D8 Use data8/SFBR 23
When this bit is set, SFBR is used instead of the data8
value during a Read-Modify-Write instruction (see
Table 6.1 ). This allows the user to add two register
values.
A[6:0] Register Address - A[6:0] [22:16]
It is possible to change register values from SCRIPTS in
read-modify-write cycles or move to/from SFBR cycles.
A[6:0] selects an 8-bit source/destination register within
the LSI53C875.
ImmD Immediate Data [15:8]
This 8-bit value is used as a second operand in logical
and arithmetic functions.
R Reserved [7:0]
6.4.2 Second Dword
Destination Address [31:0]
This field contains the 32-bit destination address where
the data to move.
6.4.3 Read-Modify-Write Cycles
During these cycles the register is read, the selected operation is
performed, and the result is written back to the source register.
The Add operation is used to increment or decrement register values (or
memory values if used in conjunction with a Memory-to-Register Move
operation) for use as loop counters.
Subtraction is not available when SFBR is used instead of data8 in the
instruction syntax. To subtract one value from another when using SFBR,
first XOR the value to subtract (subtrahend) with 0xFF, and add 1 to the
resulting value. This creates the 2’s complement of the subtrahend. The
two values are then added to obtain the difference.