Avago Technologies LSI8751D - Manual (Page 18)

1-4 General Description
1.1 Package and Feature Options
The LSI53C875 is available in three versions with different packaging
and feature options. The LSI53C875 is packaged in a 160-pin Plastic
Quad Flat Pack (PQFP). The LSI53C875J is identical to the LSI53C875
with additional pins that support JTAG boundary scan testing. The JTAG
boundary scan signals replace the TESTIN, MAC/_TESTOUT, BIG_LIT/,
and SDIRP1 pins.
The LSI53C875N includes all of the signals in the LSI53C875, with the
addition of the JTAG pins and four additional signals for extended parity
checking and generation. It is packaged in a 208-pin PQFP.
The LSI53C875JB is identical to the LSI53C875J, but is packaged in a
169-pin Ball Grid Array (BGA). The LSI53C875E, LSI53C875JE, and
LSI53C875JBE have been upgraded to include the power management
features.
1.2 Benefits of Ultra SCSI
Ultra SCSI is an extension of the SCSI-3 standard that expands the
bandwidth of the SCSI bus and allows faster synchronous SCSI transfer
rates. When enabled, Ultra SCSI performs 20 megatransfers during an
I/O operation, resulting in approximately twice the synchronous transfer
rates of fast SCSI-2. The LSI53C875 can perform 8-bit, Ultra SCSI
synchronous transfers as fast as 20 Mbytes/s. This advantage is most
noticeable in heavily loaded systems, or large block size requirements,
such as video on-demand and image processing.
An advantage of Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The LSI53C875 is compatible with all existing LSI53C825 and
LSI53C825A software; the only changes required are to enable the chip
to perform synchronous negotiations for Ultra SCSI rates. The
LSI53C875 can use the same board socket as an LSI53C825, with the
addition of an 80 MHz SCLK or enabling the internal SCSI clock doubler
to provide the correct frequency when transferring synchronous SCSI
data at 50 nanosecond transfer rates. Some changes to existing cabling
or system designs may be needed to maintain signal integrity at Ultra
SCSI synchronous transfer rates. These design issues are discussed in
Chapter 2, “Functional Description.”