Avago Technologies LSI8751D - Manual (Page 210)

6-14 Instruction Set of the I/O Processor
If reselected, the LSI53C875 fetches the next instruction
from the address pointed to by the 32-bit jump address
field stored in the
DMA Next Address (DNAD) register.
Manually set the LSI53C875 to Initiator mode when it is
reselected.
If the CPU sets the SIGP bit in the Interrupt Status
(ISTAT) register, the LSI53C875 aborts the Wait Select
instruction and fetches the next instruction from the
address pointed to by the 32-bit jump address field stored
in the
DMA Next Address (DNAD) register.
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
SCSI Output Control Latch
(SOCL) register are set. Do not set SACK/ or SATN/
except for testing purposes. When the target bit is set,
the corresponding bit in the
SCSI Control Zero (SCNTL0)
register is also set. When the carry bit is set, the
corresponding bit in the Arithmetic Logic Unit (ALU) is
set.
Note: None of the signals are set on the SCSI bus in the Target
mode.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output Con-
trol Latch (SOCL) register. Do not set SACK/ or SATN/
except for testing purposes. When the target bit is
cleared, the corresponding bit in the
SCSI Control Zero
(SCNTL0) register is cleared. When the carry bit is
cleared, the corresponding bit in the ALU is cleared.
Note: None of the signals are cleared on the SCSI bus in the
Target mode.
Figure 6.3 illustrates the I/O Instruction register.