Avago Technologies LSI8751D - Manual (Page 80)

3-16 PCI Functional Description
R Reserved 11
DT[1:0] DEVSEL/Timing [10:9]
These bits encode the timing of DEVSEL/. These are
encoded as
These bits are read only and should indicate the slowest
time that a device asserts DEVSEL/ for any bus
command except Configuration Read and Configuration
Write. The LSI53C875 supports a value of 0b01.
DPR Data Parity Reported 8
This bit is set when the following conditions are met:
•
The bus agent asserted PERR/ itself or observed
PERR/ asserted.
•
The agent setting this bit acted as the bus master for
the operation in which the error occurred.
•
The Parity Error Response bit in the Command
register is set.
R Reserved [7:5]
NC New Capabilities 4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
R Reserved [3:0]
0b00 fast
0b01 medium
0b10 slow
0b11 reserved