Figure4.2 lsi53c875j pin diagram, Lsi53c875j pin diagram – Avago Technologies LSI8751D User Manual
Page 95
4-3
Figure 4.2
LSI53C875J Pin Diagram
C_BE3/
AD23
AD22
V
DD-I
AD18
C_BE2/
IRDY/
V
SS
STOP/
PAR/
V
SS
AD15
AD11
V
SS
AD8
C_BE0/
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
36
37
38
39
40
AD17
V
SS
V
SS
V
DD-I
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
IDSEL
V
SS
AD20
V
SS
AD16
FRAME/
V
DD-I
V
SS
C_BE1/
AD13
AD12
AD9
AD21
AD19
TRDY/
DEVSEL/
PERR/
AD14
AD10
AD7
SDIR7
V
DD
SD13/
SD15/
SD1/
SD4/
V
SS-S
SD6/
V
SS-S
SRST/
SSEL/
V
SS-S
SD9/
V
DD
SDIR8
SDIR9
120
118
116
114
112
110
108
106
104
102
100
98
96
94
92
90
88
86
85
84
83
82
81
V
SS-S
SD3/
SI_O/
V
SS-S
119
117
115
113
111
109
107
105
103
101
99
97
95
93
91
89
87
SDIRP0
SD12/
V
SS-S
SD0/
SD2/
SD5/
SATN/
SBSY/
SMSG/
SREQ/
SD8/
SD11/
SD14/
SDP1/
SD7/
SDP0/
SACK/
SC_D/
SD10/
SDIR10
AD6
AD5
V
DD-I
V
SS
V
DD-C
V
SS-C
TMS
TDO
MAD4
MAD2
MAD0
GPIO2_MAS2/
V
DD
RSTDIR
BSYDIR
V
SS
IRQ/
GPIO1_MASTER/
GPIO4
TGS
V
SS
AD4
AD2
AD0
GPIO0_FETCH/
SCLK
MAD5
V
DD
MAD1
GPIO3
DIFFSENS
SELDIR
AD3
AD1
MAD7
MAD6
MAD3
V
SS
IGS
V
SS
SDIR3
SDIR2
TCK
V
SS
SDIR12
MAS1/
TDI
CLK
V
SS-C
GNT/
V
DD-C
AD31
AD30
AD28
121
123
125
127
129
131
133
135
137
139
141
143
144
145
146
147
148
150
152
154
156
158
SDIR5
MWE/
MCE/
V
SS
AD29
AD27
AD26
AD24
160
AD25
122
124
126
128
130
132
134
136
138
140
142
149
151
153
155
157
159
SDIR6
SDIR4
SDIR0
SDIR15
SDIR13
V
DD
MOE/
RST/
SDIR1
V
DD
SDIR14
MAS0/
SERR/
REQ/
V
DD-I
V
SS
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
76
77
78
79
80
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
SDIR11
LSI53C875J (JTAG)
PCI to SCSI I/O Processor
160-Pin
Quad Flat Pack
(Top View)
Note: The decoupling capacitor arrangement shown above is recommended to maximize
the benefits of the internal split ground system. Capacitor values between 0.01 and
0.1
µ
F should provide adequate noise isolation. Because of the number of high
current drivers on the LSI53C875, a multilayer PC board with power and ground
planes is required.