7 memory read multiple command, Memory read multiple command – Avago Technologies LSI8751D User Manual
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PCI Cache Mode
3-9
1.
The CLSE (Cache Line Size Enable, bit 7,
register) and ERL (Enable Read Line, bit 3,
register) bit are set.
2.
The
register must contain a legal burst size value
(2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to
the
burst size.
3.
The number of bytes to be transferred at the time a cache boundary
has been reached is equal to or greater than the
burst size.
4.
The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
3.2.7 Memory Read Multiple Command
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The LSI53C875 supports PCI Read
Multiple functionality and issues Read Multiple commands on the PCI
bus when the Read Multiple Mode is enabled. This mode is enabled by
setting bit 2 (ERMP) of the
register. If cache mode
is enabled, a Read Multiple command is issued on all read cycles, except
opcode fetches, when the following conditions are met:
1.
The CLSE bit (Cache Line Size Enable, bit 7,
register) and the ERMP bit (Enable Read Multiple, bit 2,
register) are set.
2.
The
register contains a legal burst size value (2, 4,
8, 16, 32, 64, or 128) and that value is less than or equal to the
burst size.
3.
The number of bytes to be transferred at the time a cache boundary
is reached must be at least twice the full cache line size.
4.
The chip is aligned to a cache line boundary.
When these conditions are met, the chip issues a Read Multiple
command instead of a Memory Read during all PCI read cycles.