Avago Technologies LSI8751D User Manual
Page 45
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PCI Cache Mode
2-21
To interface the LSI53C875 to the SN75976A, connect the DIR pins, as
well as IGS and TGS, of the LSI53C875 directly to the transceiver
enables (nDE/RE/). These signals control the direction of the channels
on the SN75976A.
The SCSI bidirectional control and data pins (SD[7:0]/, SDP0/, REQ/,
ACK/, MSG/, I_O/, C_D/, and ATN/) of the LSI53C875 connect to the
bidirectional data pins (nA) of the SN75976A with a pull-up resistor. The
pull-up value should be no lower than the transceiver I
OL
can tolerate,
but not so high as to cause RC timing problems. The three remaining
pins, SEL/, BSY/, and RST/ are connected to the SN75976A with a
pull-down resistor. The pull-down resistors are required when the pins
(nA) of the SN75976A are configured as inputs. When the data pins are
inputs, the resistors provide a bias voltage to both the LSI53C875 pins
(SEL/, BSY/, and RST/) and the SN75976A data pins. Because the SEL/,
BSY/, and RST/ pins on the LSI53C875 are inputs only, this configuration
allows for the SEL/, BSY/, and RST/ SCSI signals to be asserted on the
SCSI bus. The differential pairs on the SCSI bus are reversed when
connected to the SN75976A, due to the active low nature of the SCSI
bus.
Note:
The SN75976A differential transceiver must be used to
achieve Ultra SCSI transfer rates.
8-Bit/16-Bit SCSI and the Differential Interface – In an 8-bit SCSI
bus, the SD[15:8] pins on the LSI53C875 should be pulled up with a
1.5 k
Ω
resistor or terminated like the rest of the SCSI bus lines. This is
very important, as errors may occur during reselection if these lines are
left floating. In the LSI53C875J and LSI53C875JB, the SDIRP1 pin is
replaced by the TCK JTAG signal. If the device is used in a wide
differential system, use the SDIRP0 pin to control the direction of the
differential transceiver for both the SP0 and SP1 signals. The SDIRP0
signal is capable of driving both direction inputs from a transceiver.