Avago Technologies LSI8751D - Manual (Page 10)

x Contents
Index
Customer Feedback
Figures
1.1 LSI53C875 External Memory Interface 1-2
1.2 LSI53C875 Chip Block Diagram 1-3
2.1 DMA FIFO Sections 2-15
2.2 LSI53C875 Host Interface Data Paths 2-16
2.3 Differential Wiring Diagram 2-22
2.4 Regulated Termination 2-24
2.5 Determining the Synchronous Transfer Rate 2-26
2.6 Block Move and Chained Block Move Instructions 2-35
4.1 LSI53C875 Pin Diagram 4-2
4.2 LSI53C875J Pin Diagram 4-3
4.3 LSI53C875N Pin Diagram 4-4
4.4 LSI53C875JB Pin Diagram (Top View) 4-5
4.5 LSI53C875 Functional Signal Grouping 4-9
6.1 SCRIPTS Overview 6-4
6.2 Block Move Instruction Register 6-7
6.3 I/O Instruction Register 6-15
6.4 Read/Write Instruction Register 6-23
6.5 Transfer Control Instructions 6-28
6.6 Memory Move Instruction 6-36
6.7 Load and Store Instruction Format 6-40
7.1 Rise and Fall Time Test Conditions 7-8
7.2 SCSI Input Filtering 7-8
7.3 Hysteresis of SCSI Receiver 7-9
7.4 Input Current as a Function of Input Voltage 7-9
7.5 Output Current as Function of Output Voltage 7-10
7.6 Clock Waveforms 7-11
7.7 Reset Input 7-12
7.8 Interrupt Output 7-13
7.9 PCI Configuration Register Read 7-15
7.10 PCI Configuration Register Write 7-16
7.11 Operating Register/SCRIPTS RAM Read 7-17