Avago Technologies LSI8751D - Manual (Page 128)

5-12 SCSI Operating Registers
Register: 0x03 (0x83)
SCSI Control Three (SCNTL3)
Read/Write
ULTRA Ultra Enable 7
Setting this bit enables Ultra SCSI synchronous SCSI
transfers in systems that have an 80 MHz clock. The
default value of this bit is 0. This bit should remain
cleared in systems that have a 40 MHz clock, unless the
SCSI clock doubler is used to increase the SCLK
frequency to at least 80 MHz.
When this bit is set, the signal filtering period for SREQ/
and SACK/ automatically changes to 15 ns, regardless of
the value of the Extend REQ/ACK Filtering bit in the
SCSI
Test Two (STEST2) register.
SCF[2:0] Synchronous Clock Conversion Factor [6:4]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the
synchronous SCSI control logic. Write these to the same
value as the Clock Conversion Factor bits below unless
fast SCSI operation is desired. See the
SCSI Transfer
(SXFER) register description for examples of how the
SCF bits are used to calculate synchronous transfer
periods. See the table under the description of bits [7:5]
of the
SCSI Transfer (SXFER) register for the valid
combinations.
Note: To migrate from a Fast SCSI-2 system with a 40 MHz
clock, divide the clock by a factor of two or more to achieve
the same synchronous transfer rate in a system with an
80 MHz clock. For additional information on how the
synchronous transfer rate is determined, refer to
Chapter 2,
“Functional Description.”
EWS Enable Wide SCSI 3
When this bit is clear, all information transfer phases are
assumed to be eight bits, transmitted on SD[7:0]/, SDP0/.
When this bit is asserted, data transfers are done 16 bits
7 6 4 3 2 0
ULTRA SCF[2:0] EWS CCF[2:0]
0 0 0 0 0 0 0 0