Avago Technologies LSI8751D - Manual (Page 264)

7-28 Instruction Set of the I/O Processor
Figure 7.19 Burst Read
1 2 3 4 5 6 7 8 9
t
9
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by LSI53C875)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by LSI53C875-
t
10
t
6
t
3
t
4
t
5
Addr
Out
Addr
Out
t
2 t
3
Data In
BE CMD
t
3
t
3
CMD
Out In
t
2
t
1
t
3
t
3
t
2 t
1
t
3
for Address,
by Target for Data)
Addr, Target-Data