Avago Technologies LSI8751D - Manual (Page 68)

3-4 PCI Functional Description
3.1.1.3 Memory Read
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
3.1.1.4 Memory Read Multiple
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
3.1.1.5 Memory Read Line
The Memory Read command reads data from an agent mapped in
memory address space. All 32 address bits are decoded.
3.1.1.6 Memory Write
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
3.1.1.7 Memory Write and Invalidate
The Memory Write command writes data to an agent when mapped in
memory address space. All 32 address bits are decoded.
3.2 PCI Cache Mode
The LSI53C875 supports the PCI specification for an 8-bit Cache Line
Size register located in the PCI configuration space. The Cache Line
Size register provides the ability to sense and react to nonaligned
addresses corresponding to cache line boundaries. In conjunction with
the
Cache Line Size register, the PCI commands Read Line, Read
Multiple, and Write and Invalidate are each software enabled or disabled
to allow the user full flexibility in using these commands.
3.2.1 Support for PCI Cache Line Size Register
The LSI53C875 supports the PCI specification for an 8-bit Cache Line
Size register in PCI configuration space. It can sense and react to
nonaligned addresses corresponding to cache line boundaries.