Avago Technologies LSI8751D - Manual (Page 21)

LSI53C875 Benefits Summary 1-7
1.4.2 PCI Performance
To improve PCI performance, the LSI53C875:
•
Complies with PCI 2.1 specification.
•
Bursts 2, 4, 8, 16, 32, 64, or 128 Dwords across PCI bus.
•
Supports 32-bit word data bursts with variable burst lengths.
•
Prefetches up to 8 Dwords of SCRIPTS instructions.
•
Bursts SCRIPTS opcode fetches across the PCI bus.
•
Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz).
•
Supports PCI Cache Line Size register.
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
1.4.3 Integration
The following features ease integration of the LSI53C875 into a system:
•
3.3 V/5 V PCI interface.
•
Full 32-bit PCI DMA bus master.
•
Memory Move instructions allow use as a third-party PCI bus DMA
controller.
•
High-performance SCSI core.
•
Integrated SCRIPTS processor.
1.4.4 Ease of Use
The following features of the LSI53C875 make the device user friendly:
•
Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS
storage.
•
Direct PCI to SCSI connection.
•
Reduced SCSI development effort.
•
Easily adapted to the Advanced SCSI Protocol Interface (ASPI) or
the ANSI Common Access Method (CAM), with SDMS software.