Avago Technologies LSI8751D - Manual (Page 65)

LSI53C875/875E PCI to Ultra SCSI I/O Processor 3-1
Chapter 3
PCI Functional
Description
This chapter is divided into the following sections:
•
Section 3.1, “PCI Addressing”
•
Section 3.2, “PCI Cache Mode”
•
Section 3.3, “Configuration Registers”
3.1 PCI Addressing
There are three types of PCI-defined address space:
•
Configuration space
•
Memory space
•
I/O space
The configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each “slot” or “stub” on the bus. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order addresses select a specific 8-bit
register. AD[10:8] are decoded as well, but they must be zero or the
LSI53C875 does not respond. According to the PCI specification,
AD[10:8] are reserved for multifunction devices. The host processor uses
the PCI configuration space to initialize the LSI53C875.
The lower 128 bytes of the LSI53C875 configuration space holds system
parameters while the upper 128 bytes map into the LSI53C875 operating
registers. For all PCI cycles except configuration cycles, the LSI53C875
registers are located on the 256-byte block boundary defined by the base