Avago Technologies LSI8751D - Manual (Page 169)

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COM LSI53C700 Family Compatibility 0
When the COM bit is cleared, the LSI53C875 behaves in
a manner compatible with the LSI53C700 family;
selection/reselection IDs are stored in both the
SCSI
Selector ID (SSID) and SCSI First Byte Received (SFBR)
registers.
When this bit is set, the ID is stored only in the SCSI
Selector ID (SSID) register, protecting the SFBR from
being overwritten if a selection/reselection occurs during
a DMA register-to-register operation. This bit is not
affected by a software reset.
Register: 0x3C–0x3F (0xBC–0xBF)
Adder Sum Output (ADDER)
Read Only
ADDER Adder Sum Output [31:0]
This register contains the output of the internal adder,
and is used primarily for test purposes. The power-up
value for this register is indeterminate.
Register: 0x40 (0xC0)
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status Zero
(SIST0) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, see Chapter 2, “Functional
Description.”
31 0
ADDER
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0