Avago Technologies LSI8751D - Manual (Page 268)

7-32 Instruction Set of the I/O Processor
7.4.3 External Memory Timing
Figure 7.21 through Figure 7.30 describe LSI53C875 External Memory
timing.
Figure 7.21 Read Cycle, Normal/Fast Memory (
≥
64 Kbytes), Single Byte Access
CLK
MAD
(Addr driven by LSI53C875;
Data driven by memory)
MAS2/
(Driven by LSI53C875)
MAS1/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
1 2 3 4 5 6 7 8 9
High Order
Address
Middle Order
Address
Low Order
Address
MAS0/
(Driven by LSI53C875)
t
11
t
12
t
13
t
15f
t
14f
t
13f