Avago Technologies LSI8751D - Manual (Page 78)

3-14 PCI Functional Description
R Reserved [15:9]
SERR/ Enable 8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors.
R Reserved 7
Enable Parity Error Response 6
This bit allows the LSI53C875 to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled. The LSI53C875 always
generates parity for the PCI bus.
R Reserved 5
WIE Write and Invalidate Mode 4
This bit allows the LSI53C875 to generate memory write
and invalidate commands on the PCI bus. The WIE bit in
the DMA Control (DCNTL) register must also be set for
the device to generate Write and Invalidate commands.
For more information on these conditions, refer to the
section
Section 3.2.5, “Memory Write and Invalidate
Command.” To enable Write and Invalidate Mode, set
bit 0 in the Chip Test Three (CTEST3) register (operating
register set).
R Reserved 3
EBM Enable Bus Mastering 2
This bit controls the ability of the LSI53C875 to act as a
master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the LSI53C875 to behave as a bus
master. The LSI53C875 must be a bus master in order
to fetch SCRIPTS instructions and transfer data.
EMS Enable Memory Space 1
This bit controls the ability of the LSI53C875 to respond
to Memory Space accesses. A value of zero disables the
device response. A value of one allows the LSI53C875 to
respond to Memory Space accesses at the address spec-
ified by
Base Address One (Memory) .