Avago Technologies LSI8751D - Manual (Page 140)

5-24 SCSI Operating Registers
MDPE Master Data Parity Error 6
This bit is set when the LSI53C875 as a master detects
a data parity error, or a target device signals a parity error
during a data phase. This bit is completely disabled by
the Master Parity Error Enable bit (bit 3 of
Chip Test Four
(CTEST4) ).
BF Bus Fault 5
This bit is set when a PCI bus fault condition is detected.
A PCI bus fault can only occur when the LSI53C875 is
bus master, and is defined as a cycle that ends with a
Bad Address or Target Abort Condition.
ABRT Aborted 4
This bit is set when an abort condition occurs. An abort
condition occurs when a software abort command is
issued by setting bit 7 of the
Interrupt Status (ISTAT)
register.
SSI Single Step Interrupt 3
If the Single Step Mode bit in the DMA Control (DCNTL)
register is set, this bit is set and an interrupt is generated
after successful execution of each SCRIPTS instruction.
SIR SCRIPTS Interrupt Instruction Received 2
This status bit is set whenever an Interrupt instruction is
evaluated as true.
EBPI Extended Byte Parity Error Interrupt 1
(LSI53C875N only)
This bit is set whenever the LSI53C875 detects a parity
error on one of the four additional parity pins on the
LSI53C875N.
IID Illegal Instruction Detected 0
This status bit is set any time an illegal or reserved
instruction opcode is detected, whether the LSI53C875 is
operating in single step mode or automatically executing
SCSI SCRIPTS.
Any of the following conditions during instruction
execution also set this bit:
•
The LSI53C875 is executing a Wait Disconnect
instruction and the SCSI REQ line is asserted without
a disconnect occurring.