Avago Technologies LSI8751D - Manual (Page 311)

Index IX-7
select with SATN/ on a start sequence bit 5-4
selected bit 5-54
,
5-57
selection or reselection time-out bit 5-56
,
5-59
selection response logic test bits 5-71
semaphore bit 5-32
SFBR register 5-20
shadow register test mode bit 5-40
SI_O/ status bit 5-23
SIDL least significant byte full bit 5-26
SIDL most significant byte full bit 5-29
SIDL register 5-77
SIEN0 register 5-53
SIEN1 register 5-55
SIGP bit 5-32
,
5-36
single step interrupt bit 5-24
,
5-50
single step mode bit 5-51
single-ended operation 2-19
SIST0 register 5-56
SIST1 register 5-59
SLPAR high byte enable 5-10
SLPAR mode bit 5-10
SLPAR register 5-60
SMSG/ status bit 5-23
SOCL least significant byte full bit 5-26
SOCL register 5-21
SODL most significant byte full bit 5-29
SODL register 5-78
SODR least significant byte full bit 5-26
SODR most significant byte full bit 5-29
software reset bit 5-32
source I/O memory enable bit 5-48
SREQ/ status bit 5-22
SSEL/ status bit 5-22
SSID register 5-22
SSTAT0 register 5-26
SSTAT1 register 5-27
SSTAT2 register 5-29
stacked interrupts 2-32
start DMA operation bit 5-52
start SCSI transfer 5-8
start sequence bits 5-4
STEST0 register 5-70
STEST1 register 5-72
STEST2 register 5-73
STEST3 register 5-75
STIME0 register 5-64
STIME1 register 5-66
storage device management system (SDMS) 2-3
SWIDE register 5-61
SXFER register 5-15
synchronous clock conversion factor bits 5-12
synchronous data transfer rates 2-26
synchronous transfer period bits 5-15
T
target mode bit 5-6
TEMP register 5-38
temporary register 5-38
termination 2-23
timer test mode bit 5-76
timings
PCI 7-50
SCSI 7-51
TolerANT 7-7
TolerANT enable bit 5-75
TolerANT technology 1-5
benefits 1-5
extend SREQ/SACK filtering bit 5-74
TolerANT enable bit 5-75
totem pole output 4-6
transfer control instructions 6-26
and SCRIPTS instruction prefetching 2-6
transfer rate 1-6
synchronous 2-26
U
Ultra
Ultra enable bit 5-12
Ultra SCSI
benefits 1-4
designing an Ultra SCSI system 2-4
synchronous transfer period bits 5-15
unexpected disconnect bit 5-55
,
5-58
W
WATN/ bit 5-4
wide SCSI
always wide SCSI bit 5-74
chained block moves 2-34
chained mode bit 5-9
enable wide SCSI bit 5-12
SWIDE register 5-61
wide SCSI receive bit 5-11
wide SCSI send bit 5-10
wide SCSI receive bit 5-11
wide SCSI send bit 5-10
won arbitration bit 5-27
write and invalidate enable bit 5-38