Avago Technologies LSI8751D - Manual (Page 66)

3-2 PCI Functional Description
address assigned through the configured register. The LSI53C875
operating registers are available in both the upper and lower 128-byte
portions of the 256-byte space selected.
At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C875, the upper 24 bits of the address are selected)
for memory and I/O accesses. On every access, the LSI53C875
compares its assigned base addresses with the value on the
Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C875 and the low-order eight bits
define the register to be accessed. A decode of C_BE/[3:0] determines
which registers and what type of access is to be performed.
The PCI specification defines memory space as a contiguous 32-bit
memory address that is shared by all system resources, including the
LSI53C875.
Base Address One (Memory) determines which 256-byte
memory area this device occupies.
The PCI specification defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the LSI53C875.
Base Address Zero (I/O) determines which 256-byte I/O area this device
occupies.
3.1.1 PCI Bus Commands and Functions Supported
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus command encoding and types appear
in
Table 3.1 .