Avago Technologies LSI8751D - Manual (Page 263)

PCI and External Memory Interface Timing Diagrams 7-27
Figure 7.18 Back-to-Back Write
Addr
Out
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by System)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by LSI53C875)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by LSI53C875)
t
9
t
10
t
6
t
4
t
5
t
3
CMD
t
3
t
3
t
3
t
3
t
2
t
2
t
1
Data
Out
Addr
Out
Data
Out
BE CMD BE
t
3
t
3
t
3
t
1
t
2