Avago Technologies LSI8751D - Manual (Page 11)

Contents xi
7.12 Operating Register/SCRIPTS RAM Write 7-18
7.13 External Memory Read 7-20
7.14 External Memory Write 7-22
7.15 Opcode Fetch, Nonburst 7-24
7.16 Burst Opcode Fetch 7-25
7.17 Back-to-Back Read 7-26
7.18 Back-to-Back Write 7-27
7.19 Burst Read 7-28
7.20 Burst Write 7-30
7.21 Read Cycle, Normal/Fast Memory ( 64 Kbytes),
Single Byte Access
7-32
7.22 Write Cycle, Normal/Fast Memory ( 64 Kbytes),
Single Byte Access
7-34
7.23 Read Cycle, Normal/Fast Memory ( 64 Kbyte),
Multiple Byte Access
7-36
7.24 Write Cycle, Normal/Fast Memory ( 64 Kbyte),
Multiple Byte Access
7-38
7.25 Read Cycle, Slow Memory ( 64 Kbyte) 7-40
7.26 Write Cycle, Slow Memory ( 64 Kbyte) 7-42
7.27 Read Cycle, Normal/Fast Memory ( 64 Kbyte) 7-44
7.28 Write Cycle, Normal/Fast Memory ( 64 Kbyte) 7-45
7.29 Read Cycle, Slow Memory (£ 64 Kbyte) 7-46
7.30 Write Cycle, Slow Memory (£ 64 Kbyte) 7-48
7.31 Initiator Asynchronous Send 7-51
7.32 Initiator Asynchronous Receive 7-52
7.33 Target Asynchronous Send 7-52
7.34 Target Asynchronous Receive 7-53
7.35 Initiator and Target Synchronous Transfer 7-53
7.36 169-Pin PBGA (GV) Mechanical Drawing 7-58
7.37 160-pin PQFP (P3) Mechanical Drawing 7-59
B.1 64 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 256 Kbyte Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4