Avago Technologies LSI8751D - Manual (Page 259)

PCI and External Memory Interface Timing Diagrams 7-23
Figure 7.14 External Memory Write (Cont.)
11 12 13 14 15 16 17 18 19 20
t
2
t
2
21
t
1
t
3
t
3
Data In
Byte Enable
In
Data Out
t
20
t
23
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
LSI53C875-Data)
LSI53C875-Data)
MAD
(Driven by LSI53C875)
GPIO2_MAS2/
(Driven by LSI53C875)
MAS1/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
MAS0/
(Driven by LSI53C875)
t
2
t
2
t
22
t
21
t
26
t
24
t
25