Avago Technologies LSI8751D - Manual (Page 13)

Contents xiii
7.1 Absolute Maximum Stress Ratings 7-2
7.2 Operating Conditions 7-2
7.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/ 7-3
7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,
SSEL/, SRST/
7-3
7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS, BIG_LIT/
7-3
7.6 Capacitance 7-4
7.7 Output Signals—MAC/_TESTOUT, REQ/ 7-4
7.8 Output Signals—IRQ/, SDIR[15:0], SDIRP0, SDIRP1,
BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/,
MOE/, MWE/
7-4
7.9 Output Signal—SERR/ 7-4
7.10 Bidirectional Signals—AD[31:0], C_BE[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
7-5
7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/,
GPIO2_MAS2/, GPIO3, GPIO4
7-5
7.12 Bidirectional Signals—MAD[7:0] 7-6
7.13 Input Signals—TDI, TMS, TCK (LSI53C875J,
LSI53C875JB, LSI53C875N Only)
7-6
7.14 Output Signal—TDO (LSI53C875, LSI53C875JB,
LSI53C875N Only)
7-6
7.15 TolerANT Technology Electrical Characteristics 7-7
7.16 Clock Timing 7-11
7.17 Reset Input 7-12
7.18 Interrupt Output 7-13
7.19 LSI53C875 PCI and External Memory Interface Timing 7-50
7.20 Initiator Asynchronous Send 7-51
7.21 Initiator Asynchronous Receive 7-52
7.22 Target Asynchronous Send 7-52
7.23 Target Asynchronous Receive 7-53
7.24 SCSI-1 Transfers (SE, 5.0 Mbytes/s) 7-54
7.25 SCSI-1 Transfers (Differential, 4.17 Mbytes/s) 7-54
7.26 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 40 MHz Clock
7-55
7.27 SCSI-2 Fast Transfers 10.0 Mbytes/s (8-Bit Transfers)
or 20.0 Mbytes/s (16-Bit Transfers), 50 MHz Clock
7-55
7.28 Ultra SCSI SE Transfers 20.0 Mbytes/s (8-Bit Transfers)
or 40.0 Mbytes/s (16-Bit Transfers), 80 MHz Clock
7-56