Table 2.4 scsi parity errors and interrupts, 8 dma fifo, Figure2.1 dma fifo sections – Avago Technologies LSI8751D User Manual
Page 39: Dma fifo, Dma fifo sections, Scsi parity errors and interrupts, Table 2.4
PCI Cache Mode
2-15
2.5.8 DMA FIFO
The DMA FIFO is 4 bytes wide by 134 transfers deep. The DMA FIFO
is illustrated in
. To assure compatibility with older products in
the LSI53C8XX family, the DMA FIFO size may be set to 88 bytes by
setting the DMA FIFO Size bit, bit 5 in the
register.
Figure 2.1
DMA FIFO Sections
Table 2.4
SCSI Parity Errors and Interrupts
DPH
PAR
Description
0
0
Halts when a parity error occurs in target or initiator mode and does
not generate an interrupt.
0
1
Halts when a parity error occurs in target mode and generates an
interrupt in the target or initiator mode.
1
0
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is not generated.
1
1
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is generated.
Key:
DHP = Disable Halt on SATN/ or Parity Error (bit 5,
.
PAR = Parity Error (bit 0,
SCSI Interrupt Enable One (SIEN1)
.
134
Transfers
Deep
.
.
.
.
.
.
32 Bytes Wide
8 Bits
Byte Lane 3
8 Bits
Byte Lane 2
8 Bits
Byte Lane 1
8 Bits
Byte Lane 0