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Chapter5 scsi operating registers, Chapter 5, scsi operating registers, Descr – Avago Technologies LSI8751D User Manual

Page 117: Chapter 5, Scsi operating registers, Chapter 5, “scsi operating registers, Chapter 5 scsi operating registers

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LSI53C875/875E PCI to Ultra SCSI I/O Processor

5-1

Chapter 5
SCSI Operating
Registers

This section contains descriptions of all LSI53C875 operating registers.

Table 5.1

lists registers by operating and configuration addresses. The

terms “set” and “assert” are used to refer to bits that are programmed to
a binary one. Similarly, the terms “deassert,” “clear,” and “reset” are used
to refer to bits that are programmed to a binary zero. Any bits marked as
reserved should always be written to zero; mask all information read from
them. Reserved bit functions may be changed at any time. Unless
otherwise indicated, all bits in registers are active HIGH, that is, the
feature is enabled by setting the bit. The bottom row of every register
diagram shows the default register values, which are enabled after the
chip is powered on or reset.

Note:

The only register that the host CPU can access while the
LSI53C875 is executing SCRIPTS is the

Interrupt Status

(ISTAT)

register. Attempts to access other registers

interferes with the operation of the chip. However, all
operating registers are accessible with SCRIPTS. All read
data is synchronized and stable when presented to the PCI
bus. The LSI53C875 cannot fetch SCRIPTS instructions
from the operating register space. Instructions must be
fetched from system memory or the internal SCRIPTS
RAM.

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