Avago Technologies LSI8751D User Manual
Page 181
5-65
SEL
Selection Time-Out
[3:0]
These bits select the SCSI selection/reselection time-out
period. When this timing (plus the 200
µ
s selection abort
time) is exceeded, the STO bit in the
register is set. For a more detailed
explanation of interrupts, refer to
HTH [7:4]
SEL [3:0]
GEN [3:0]
Minimum Time-out
1
1. These values will be correct if the CCF bits in the
register are set according to the valid combinations in the bit
description.
40 MHz/80 MHz
50 MHz
0000
Disabled
Disabled
0001
125
µ
s
100
µ
s
0010
250
µ
s
200
µ
s
0011
500
µ
s
400
µ
s
0100
1 ms
800
µ
s
0101
2 ms
1.6 ms
0110
4 ms
3.2 ms
0111
8 ms
6.4 ms
1000
16 ms
12.8 ms
1001
32 ms
25.6 ms
1010
64 ms
51.2 ms
1011
128 ms
102.4 ms
1100
256 ms
204.8 ms
1101
512 ms
409.6 ms
1110
1.024 s
819.2 ms
1111
2.048 s
1.6384 s
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