Avago Technologies LSI8751D - Manual (Page 34)

2-10 Functional Description
2.5.4 JTAG Boundary Scan Testing
The LSI53C875J/LSI53C875N/LSI53C875JB include support for JTAG
boundary scan testing in accordance with the IEEE 1149.1 specification
with one exception, which is discussed in this section. The device
accepts all required boundary scan instructions, including the optional
CLAMP, HIGH-Z, and IDCODE instructions.
The LSI53C875J/LSI53C875N/LSI53C875JB use an 8-bit instruction
register to support all boundary scan instructions. The data registers
included in the device are the Boundary Data register, the IDCODE
register, and the Bypass register. This device can handle a 10 MHz TCK
frequency for TDO and TDI.
Due to design constraints, the RST/ pin (system reset) always 3-states
the SCSI pins when it is asserted. Boundary scan logic does not control
this action, and this is not compliant with the specification. There are two
solutions that resolve this issue:
1. Use the RST/ pin as a boundary scan compliance pin. When the pin
is deasserted, the device is boundary scan compliant and when
asserted, the device is noncompliant. To maintain compliance the
RST/ pin must be driven high.
2. When RST/ is asserted during boundary scan testing the expected
output on the SCSI pins must be a HIGH-Z condition, and not what
is contained in the boundary scan data registers for the SCSI pin
output cells.
Because of package limitations, the LSI53C875J/LSI53C875JB replaces
the TESTIN, MAC/_TESTOUT, BIG_LIT/, and SDIRP1 signals with the
JTAG boundary scan signals. The LSI53C875N includes support for
these signals in addition to the JTAG pins.
2.5.5 Big and Little Endian Support
The LSI53C875/LSI53C875N supports both big and little endian byte
ordering through pin selection. The LSI53C875J/LSI53C875JB operate in
little endian mode only (the BIG_LIT pin is replaced by one of the JTAG
boundary scan signals). In big endian mode, the first byte of an aligned
SCSI to PCI transfer is routed to lane three and succeeding transfers are
routed to descending lanes. This mode of operation also applies to data
transfers over the add-in ROM interface. The byte of data accessed at