13 interrupt handling, Interrupt handling – Avago Technologies LSI8751D User Manual
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Functional Description
a value of 101 (binary), allowing the SCLK frequency to be divided
down by 4. This allows systems using an 80 MHz clock or the
internal clock doubler to operate at Fast SCSI-2 transfer rates as well
as Ultra SCSI rates, if needed.
•
Ultra Mode Enable bit,
register bit 7.
Setting this bit enables Ultra SCSI synchronous transfers in systems
that have an 80 MHz clock or use the internal SCSI clock doubler.
2.5.13 Interrupt Handling
The SCRIPTS processors in the LSI53C875 perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C875.
2.5.13.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit set that
indicates an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C875 asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
2.5.13.2 Registers
The registers in the LSI53C875 that are used for detecting or defining
interrupts are the
,
SCSI Interrupt Status One (SIST1)
,
,
SCSI Interrupt Enable One (SIEN1)
, and
.
ISTAT – The ISTAT register is the only register that can be accessed as
a slave during SCRIPTS operation. Therefore it is the register that is
polled when polled interrupts are used. It is also the first register that
should be read when the IRQ/ pin has been asserted in association with