Avago Technologies LSI8751D - Manual (Page 70)

3-6 PCI Functional Description
Example: Cache Line Size - 16, Current Address = 0x01 – The chip
is not aligned to a 4 Dword cache boundary (the stepping threshold), so
it issues four single Dword transfers (the first is a 3-byte transfer). At
address 0x10, the chip is aligned to a 4 Dword boundary, but not aligned
to any higher burst size boundaries that are less than the cache line size.
So, the part issues a burst of 4. At this point, the address is 0x20, and
the chip evaluates that it is aligned not only to a 4 Dword boundary, but
also to an 8 Dword boundary. It selects the highest, 8, and bursts
8 Dwords. At this point, the address is 0x40, which is a cache line size
boundary. Alignment stops, and the burst size from then on is switched
to 16.
3.2.4 Memory Move Misalignment
The LSI53C875 does not operate in a cache alignment mode when a
Memory Move instruction type is issued and the read and write
addresses are different distances from the nearest cache line boundary.
For example, if the read address is 0x21F and the write address is
0x42F, and the cache line size is 8, the addresses are byte aligned, but
they are not the same distance from the nearest cache boundary. The
read address is 1 byte from the cache boundary 0x220 and the write
address is 17 bytes from the cache boundary 0x440. In this situation, the
chip does not align to cache boundaries and operates as an LSI53C825.
3.2.5 Memory Write and Invalidate Command
The Memory Write and Invalidate command is identical to the Memory
Write command, except that it additionally guarantees a minimum
transfer of one complete cache line; that is to say, the master intends to
write all bytes within the addressed cache line in a single PCI transaction
unless interrupted by the target. This command requires implementation
of the PCI
Cache Line Size register at address 0x0C in PCI configuration
space. The LSI53C875 enables Memory Write and Invalidate cycles
when bit 0 in the
Chip Test Three (CTEST3) register (WRIE) and bit 4 in
the PCI Command register are set. When the following conditions are
met, Memory Write and Invalidate commands are issued:
1. The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register), WRIE bit (Write and Invalidate Enable, bit 0, Chip Test
Three (CTEST3) register), and PCI configuration Command register,
bit 4 are set.