Avago Technologies LSI8751D - Manual (Page 289)

SCSI Timing Diagrams 7-53
Figure 7.34 Target Asynchronous Receive
Figure 7.35 Initiator and Target Synchronous Transfer
Table 7.23 Target Asynchronous Receive
Symbol Parameter Min Max Unit
t
1
SREQ/ deasserted from SACK/ asserted 5 – ns
t
2
SREQ/ asserted from SACK/ deasserted 5 – ns
t
3
Data setup to SACK/ asserted 0 – ns
t
4
Data hold from SREQ/ deasserted 0 – ns
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/
n
n + 1
t
2
t
1
t
3
t
4
Valid n Valid n + 1
n + 1
n
SREQ/
or SACK/
Send Data
SD[15:0]/, SDP[1:0]/
Receive Data
SD[15:0]/,
SDP[1:0]/
t
3
t
4
t
1
t
2
t
5 t
6
n n + 1
Valid n Valid n + 1
Valid n Valid n + 1