Avago Technologies LSI8751D - Manual (Page 167)

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For more information on interrupts, see Chapter 2, “Functional
Description.”
Register: 0x3A (0xBA)
Scratch Byte Register (SBR)
Read/Write
This is a general purpose register. Apart from CPU access, only register
Read/Write and Memory Moves into this register will alter its contents.
The default value of this register is zero. This register was called the
DMA Watchdog Timer on previous LSI53C8XX family products.
Register: 0x3B (0xBB)
DMA Control (DCNTL)
Read/Write
CLSE Cache Line Size Enable 7
Setting this bit enables the LSI53C875 to sense and
react to cache line boundaries set up by the DMODE or
PCI
Cache Line Size register, whichever contains the
smaller value. Clearing this bit disables the cache line
size logic and the LSI53C875 monitors the cache line
size using the
DMA Mode (DMODE) register.
PFF Prefetch Flush 6
Setting this bit causes the prefetch unit to flush its
contents. The bit clears after the flush is complete.
PFEN Prefetch Enable 5
Setting this bit enables the prefetch unit if the burst size
is equal to or greater than four. For more information on
SCRIPTS instruction prefetching, see
Chapter 2, “Func-
tional Description.”
SSM Single Step Mode 4
Setting this bit causes the LSI53C875 to stop after
executing each SCRIPTS instruction, and generates a
single step interrupt. When this bit is cleared, the
LSI53C875 does not stop after each instruction. It
7 6 5 4 3 2 1 0
CLSE PFF PFEN SSM IRQM STD IRQD COM
0 0 0 0 0 0 0 0