Avago Technologies LSI8751D - Manual (Page 265)

PCI and External Memory Interface Timing Diagrams 7-29
Figure 7.19 Burst Read (Cont.)
10 11 12 13 14 15 16 17 18
CLK
GPIO0_FETCH/
GPIO1_MASTER/
REQ/
GNT/
FRAME/
C_BE/
PAR/
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by LSI53C875)
(Driven by Arbiter)
(Driven by LSI53C875)
AD/
(Driven by LSI53C875)
IRDY/
(Driven by Target)
(Driven by LSI53C875)
TRDY/
STOP/
DEVSEL/
(Driven by LSI53C875)
(Driven by Target)
(Driven by Target)
(Driven by LSI53C875-
Addr
Out
BE CMD
Out In
t
2
t
1
for Address,
by Target for Data)
Addr, Target-Data
18 19
BE
In In