Avago Technologies LSI8751D - Manual (Page 258)

7-22 Instruction Set of the I/O Processor
Figure 7.14 External Memory Write
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
1 2 3 4 5 6 7 8 9 10
LSI53C875-Data)
Byte Enable
LSI53C875-Data)
MAD
(Driven by LSI53C875)
High Order
Address
Middle Order
Address
Low Order
Address
GPIO2_MAS2/
(Driven by LSI53C875)
MAS1/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
t
1
t
2
In
t
1
t
2
t
1
t
3
t
11
Data In
t
23
t
20
t
1
Addr
In
t
1
t
1
t
2
CMD
t
12
t
13
MAS0/
(Driven by LSI53C875)