Avago Technologies LSI8751D - Manual (Page 231)

Memory Move Instructions 6-35
The SFBR is not writable using the CPU, and therefore not by a Memory
Move. However, it can be loaded using SCRIPTS Read/Write operations.
To load the SFBR with a byte stored in system memory, first move the
byte to an intermediate LSI53C875 register (for example, a SCRATCH
register), and then to the SFBR.
The same address alignment restrictions apply to register access
operations as to normal memory-to-memory transfers.
6.6.2 Second Dword
DSPS Register [31:0]
These bits contain the source address of the Memory
Move.
6.6.3 Third Dword
TEMP Register [31:0]
These bits contain the destination address for the
Memory Move.
Figure 6.6 illustrates the Memory Move instruction.