Avago Technologies LSI8751D - Manual (Page 171)

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Residual data in SCSI FIFO – starting a transfer other
than synchronous data receive with data left in the
SCSI synchronous receive FIFO.
UDC Unexpected Disconnect 2
This condition only occurs in the initiator mode. It
happens when the target to which the LSI53C875 is
connected disconnects from the SCSI bus unexpectedly.
See the SCSI Disconnect Unexpected bit in the
SCSI
Control Two (SCNTL2) register for more information on
expected versus unexpected disconnects. Any discon-
nect in low level mode causes this condition.
RST SCSI Reset Condition 1
Indicates assertion of the SRST/ signal by the LSI53C875
or any other SCSI device. This condition is edge-
triggered, so multiple interrupts cannot occur because of
a single SRST/ pulse.
PAR SCSI Parity Error 0
Indicates detection of a parity error while receiving or
sending SCSI data. See the Disable Halt on Parity Error
or SATN/ Condition bits in the
SCSI Control One
(SCNTL1) register for more information on when this
condition is actually raised.
Register: 0x41 (0xC1)
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status One
(SIST1) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, refer to Chapter 2, “Functional
Description.”
7 3 2 1 0
R STO GEN HTH
x x x x x 0 0 0