Avago Technologies LSI8751D - Manual (Page 148)

5-32 SCSI Operating Registers
2. Wait for an interrupt.
3. Read the Interrupt Status (ISTAT) register.
4. If the SCSI Interrupt Pending bit is set, then read the
SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt
Status One (SIST1) register to determine the cause
of the SCSI Interrupt and go back to Step 2.
5. If the SCSI Interrupt Pending bit is clear, and the
DMA Interrupt Pending bit is set, then write 0x00
value to this register.
6. Read the DMA Status (DSTAT) register to verify the
aborted interrupt and to see if any other interrupting
conditions have occurred.
SRST Software Reset 6
Setting this bit resets the LSI53C875. All operating
registers are cleared to their respective default values
and all SCSI signals are deasserted. Setting this bit does
not assert the SCSI RST/ signal. This reset does not
clear the LSI53C700 Family Compatibility bit or any of the
PCI configuration registers. This bit is not self-clearing; it
must be cleared to clear the reset condition (a hardware
reset also clears this bit).
SIGP Signal Process 5
SIGP is a R/W bit that can be written at any time, and
polled and reset using
Chip Test Two (CTEST2) . The
SIGP bit is used in various ways to pass a flag to or from
a running SCRIPTS instruction.
The only SCRIPTS instruction directly affected by the
SIGP bit is Wait for Selection/Reselection. Setting this bit
causes that instruction to jump to the alternate address
immediately. The instructions at the alternate jump
address should check the status of SIGP to determine
the cause of the jump. The SIGP bit is usable at any time
and is not restricted to the wait for selection/reselection
condition.
SEM Semaphore 4
The SCRIPTS processor may set this bit using a
SCRIPTS register write instruction. An external processor
may also set is while the LSI53C875 is executing a
SCRIPTS operation. This bit enables the LSI53C875 to