Avago Technologies LSI8751D - Manual (Page 199)

SCSI SCRIPTS 6-3
Each instruction consists of two or three 32-bit words. The first 32-bit
word is always loaded into the
DMA Command (DCMD) and DMA Byte
Counter (DBC) registers, the second into the DMA SCRIPTS Pointer
Save (DSPS) register. The third word, used only by Memory Move
instructions, is loaded into the Temporary (TEMP) shadow register. In an
indirect I/O or Move instruction, the first two 32-bit opcode fetches is
followed by one or two more 32-bit fetch cycles.
6.1.1 Sample Operation
This operation describes execution of a SCRIPTS instruction for a Block
Move instruction.
•
The host CPU, through programmed I/O, gives the DMA SCRIPTS
Pointer (DSP) register (in the Operating register file) the starting
address in main memory that points to a SCSI SCRIPTS program
for execution.
•
Loading the DMA SCRIPTS Pointer (DSP) register causes the
LSI53C875 to fetch its first instruction at the address just loaded.
This will be from main memory or the internal RAM, depending on
the address.
•
The LSI53C875 typically fetches two longwords (64 bits) and
decodes the high order byte of the first longword as a SCRIPTS
instruction. If the instruction is a Block Move, the lower three bytes
of the first longword are stored and interpreted as the number of
bytes to be moved. The second longword is stored and interpreted
as the 32-bit beginning address in main memory to which the move
is directed.
•
For a SCSI send operation, the LSI53C875 waits until there is
enough space in the DMA FIFO to transfer a programmable size
block of data. For a SCSI receive operation, it waits until enough
data is collected in the DMA FIFO for transfer to memory. At this
point, the LSI53C875 requests use of the PCI bus again to transfer
the data.
•
When the LSI53C875 is granted the PCI bus, it executes (as a bus
master) a burst transfer (programmable size) of data, decrements
the internally stored remaining byte count, increments the address
pointer, and then releases the PCI bus. The LSI53C875 stays off the
PCI bus until the FIFO can again hold (for a write) or has collected
(for a read) enough data to repeat the process.