Avago Technologies LSI8751D - Manual (Page 107)

4-15
Table 4.9 describes the SCSI Signals group.
Table 4.9 SCSI SIgnals
Name
Pin No.
LSI53C875,
LSI53C875J,
LSI53C875N,
LSI53C875JB Type Description
SCLK 56/73/M6 I SCSI Clock is used to derive all SCSI-related timings.
The speed of this clock is determined by the
application’s requirements. In some applications SCLK
may be sourced internally from the PCI bus clock (CLK).
If SCLK is internally sourced, then the SCLK pin should
be tied LOW.
SD[15:0]/,
SDP[1:0]/ LSI53C875,
LSI53C875J:
113, 115, 116,
117, 85, 86,
87, 89, 102,
103, 105, 106,
107, 108, 110,
111, 112, 101
LSI53C875N:
143, 145, 146,
147, 115, 116,
117, 119, 132,
133, 135, 136,
137, 138, 140,
141, 142, 131
LSI53C875JB:
D13, E10,
C13, D11, J9,
L13 K11, J10,
G10, G9, F13,
F11, F10, F9,
E12, E11, F8,
G13
I/O SCSI Data includes the following data lines and parity
signals: SD[15:0]/ (16-bit SCSI data bus), and SDP[1:0]/
(SCSI data parity bits).