Avago Technologies LSI8751D - Manual (Page 86)

3-22 PCI Functional Description
The Expansion ROM Enable bit, bit 0, is the only bit
defined in this register. This bit is used to control whether
or not the device accepts accesses to its expansion
ROM. When the bit is set, address decoding is enabled,
and a device can be used with or without an expansion
ROM depending on the system configuration. To access
the external memory interface, also set the Memory
Space bit in the
Command register.
The host system detects the size of the external memory
by first writing the
Expansion ROM Base Address register
with all ones and then reading back the register. The
LSI53C875 responds with zeros in all don’t care
locations. The ones in the remaining bits represent the
binary version of the external memory size. For example,
to indicate an external memory size of 32 Kbytes, this
register, when written with ones and read back, returns
ones in the upper 17 bits.
Register: 0x34
Capabilities Pointer
Read Only
CP Capabilities Pointer [7:0]
This register provides an offset into the function’s PCI
Configuration Space for the location of the first item in the
capabilities linked list. Only the LSI53C875E sets this
register to 0x40. The capability pointer replaces the
General Purpose Pin Control (GPCNTL) register in
earlier revisions of the LSI53C875.
7 0
CP
0 1 0 0 0 0 0 0