Avago Technologies LSI8751D User Manual
Page 124
5-8
SCSI Operating Registers
IARB
Immediate Arbitration
1
Setting this bit causes the SCSI core to immediately
begin arbitration once a Bus Free phase is detected
following an expected SCSI disconnect. This bit is useful
for multithreaded applications. The ARB[1:0] bits in
register are set for full arbitration
and selection before setting this bit.
Arbitration is retried until won. At that point, the
LSI53C875 holds BSY and SEL asserted, and waits for
a select or reselect sequence. The Immediate Arbitration
bit is cleared automatically when the selection or
reselection sequence is completed, or times out.
An unexpected disconnect condition clears IARB without
attempting arbitration. See the SCSI Disconnect
Unexpected bit (
, bit 7) for
more information on expected versus unexpected
disconnects.
During the time between the setting of the IARB bit and
the completion of a Select/Reselect instruction, DMA
interrupts are disabled. Therefore, interrupt instructions
that are issued during this time period will not execute.
It is possible to abort an immediate arbitration sequence.
First, set the Abort bit in the
register. Then one of two things eventually happens:
•
The Won Arbitration bit (
bit 2) will be set. In this case, the Immediate
Arbitration bit needs to be cleared. This completes the
abort sequence and disconnects the chip from the
SCSI bus. If it is not acceptable to go to Bus Free
phase immediately following the arbitration phase, it is
possible to perform a low level selection instead.
•
The abort completes because the LSI53C875 loses
arbitration. This is detected by the clearing of the
Immediate Arbitration bit. Do not use the Lost
Arbitration bit (
bit 3) to
detect this condition. Take no further action in this
case.
SST
Start SCSI Transfer
0
This bit is automatically set during SCRIPTS execution
and should not be used. It causes the SCSI core to begin
a SCSI transfer, including SREQ/SACK handshaking.